Representation of Negative Number and Subtraction

Representation of negative number

I was confused the first time I saw a 4 bits Parallel Full Adder, There is also some possibility that you may share the same confusion that I had. My confusion was, “What is that symbol H in a Parallel Full Adder ?”, “What is it for ?”. Later it turned out that Parallel Full Adder can also be used for subtraction, so Parallel Full Adder is somehow equivalent to a Parallel Full Subtractor.
Lets suppose that there is a positive number represented as 4 bits binary or 8 bits binary, the negative binary form of the number, is included in the table below :

Positive	4 bits	8 bits	Negative	4 bits	8 bits
0	0000	00000000	0	0000	00000000
1	0001	00000001	-1	1111	11111111
2	0010	00000010	-2	1110	11111110
3	0011	00000011	-3	1101	11111101
4	0100	00000100	-4	1100	11111100
5	0101	00000101	-5	1011	11111011
6	0110	00000110	-6	1010	11111010
7	0111	00000111	-7	1001	11111001
8	NONE	00001000	-8	1000	11111000

Table of binary representation

From the table above it can be inferred that all negative number’s binary representation have the value of 1 in its Most Significant Bits, which often called Sign Bit. So Sign Bit = 0, means that the number is positive, while Sign Bit = 1, means that the number is negative.

Parallel Full Subtractor

By doing some observation on the relationship between positive and negative number’s binary representation it is not hard, to arrive at equation E7 :
-B = not B +1 ….(E7)

Equation E8, is common arithmetic sense :
A - B = A + (-B) ….(E8)

By substituting equation E7 to equation E8, we can get equation E9 :
A – B = A + not B + 1 ….(E9)

Equation E9 is the basic thought required in order to understand how to use a Parallel Full Adder as a Parallel Full Subtractor, here is the logic in equation E10 and E11 :
{A + B = A + B + H, H = 0} ….(E10)
A – B = A + (-B) = A + not B + 1, which if H =1, is equivalent with equation E11 below
{A – B = A + not B + H, H = 1} ….(E11)

From Equation E0 and E11, it can be inferred that to make a Parallel Full Adder to become a Parallel Full Subtractor, we only need to add (not B+1) with A instead of B.

The input are vectors of bit, A (A0,A1,A2,A3) and B (B0,B1,B2,B3), with the result of vector R(R0,R1,R2,R3,R4), note that the A0,B0 and R0 are Least Significant Bits, while A3,B3 and R4 are Most Significant Bits.

Using 4bit Parallel Full Adder as 4 bit Parallel Full Subtractor.

Full Adder/Subtractor Hybrid

Full Adder/Subtraction Hybrid is a generalized use of a Parallel Full Adder as both Adder or Subtractor, depending on the Sign Bit (H). A Full Adder/Subtraction Hybrid is in fact one of the most simple Arithmetic Logic Unit in existence, with capability of Addition and Subtraction.

The logic construction of a Full Adder/Subtractor Hybrid

This is the most simple part of a Arithmetic Logic Unit

Since H is the Sign Bit, If H is true(1) the system output will be R = A - B, while if H is false(0) the system output will be R = A + B. This is done by placing XOR gates between (B0,B1,B2,B3), and the Sign Bit H, which work due to the fact that :
B xor H = B, if H=0
B xor H = not B, if H =1

More explanation on why this result in a Full Adder/Subtractor Hybrid is given in Equation E1 and E11
{A + B = A + B + H, H = 0} ….(E10)
{A – B = A + not B + H, H = 1} ….(E11)

In my later study it turn out that Full Adder is the basic part of many arithmetic logic application, including basic arithmetic like Parallel Multiplication, Parallel Division, or more advanced application (with Multiplexer and Demultiplexer included) like Float Adder, Float Subtractor, Float Multiplication and Float Division.

I will add these applications in my later posting.